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Name: microcode | Distribution: Mageia |
Version: 0.20220419 | Vendor: Mageia.Org |
Release: 1.mga8.nonfree | Build date: Sun Apr 24 21:13:22 2022 |
Group: System/Kernel and hardware | Build host: localhost |
Size: 5019193 | Source RPM: microcode-0.20220419-1.mga8.nonfree.src.rpm |
Packager: tmb <tmb> | |
Summary: Intel / AMD CPU Microcode |
Since PentiumPro, Intel CPU are made of a RISC chip and of a microcode whose purpose is to decompose "old" ia32 instruction into new RISC ones. P6 family is concerned: PPro, PII, Celeron, PIII, Celeron2. Recent kernels have the ability to update this microcode. The microcode update is volatile and needs to be uploaded on each system boot, i.e. it doesn't reflash your cpu permanently. Reboot and it reverts back to the old microcode. This package contains microcode for Intel and Amd CPUs.
Distributable
* Sun Apr 24 2022 tmb <tmb> 0.20220419-1.mga8 + Revision: 1853110 - update to Intel 20220419 release - update Amd SEV firmware - update AMD cpu microcode for processor family 17h and 19h - Update AMD fam 19h cpu microcode - update to Intel 20220207 release - Update AMD cpu microcode for processor family 19h to 2021-11-15 - Add AMD cpu microcode for processor family 19h - Update AMD SEV firmware: * version 0.17 build 46 for AMD family 17h processors with models in the range 00h to 0fh. * version 0.24 build 14 for AMD family 17h processors with models in the range 30h to 3fh. - Add AMD SEV firmware version 1.42 build 42 for AMD family 19h processors with models in the range 00h to 0fh. - update to 20210608 - update Intel microcode to 20210216 release * Fri Nov 20 2020 tmb <tmb> 0.20201118-2.mga8.nonfree + Revision: 1647992 - Update AMD SEV firmware to version 0.17 build 44 for AMD family 17h processors with models in the range 00h to 0fh. - Update AMD SEV firmware to version 0.24 build 7 for AMD family 17h processors with models in the range 30h to 3fh. * Thu Nov 19 2020 ns80 <ns80> 0.20201118-1.mga8.nonfree + Revision: 1647550 - fix Intel Microcode regression (mga#27633) * Mon Nov 16 2020 tmb <tmb> 0.20201112-1.mga8.nonfree + Revision: 1646742 - remove broken microcode for TGL-UP3 (mga#27597) - update Intel microcode to 20201112 release * Thu Nov 12 2020 ns80 <ns80> 0.20201110-1.mga8.nonfree + Revision: 1644799 - update to Intel 20201110 release for CVE-2020-869[568] (mga#27597) * Sat Jul 25 2020 ns80 <ns80> 0.20200616-2.mga8.nonfree + Revision: 1608948 - update post script (mga#26995) * Tue Jul 21 2020 ns80 <ns80> 0.20200616-1.mga8.nonfree + Revision: 1607526 - update to Intel 20200616 release for CVE-2020-0543, CVE-2020-0548, CVE-2020-0549 (mga#26783) * Mon Jul 20 2020 ns80 <ns80> 0.20200609-1.mga8.nonfree + Revision: 1607352 - update to Intel 20200609 release for CVE-2020-0543, CVE-2020-0548, CVE-2020-0549 (mga#26783) * Thu May 21 2020 tmb <tmb> 0.20200520-1.mga8.nonfree + Revision: 1586577 - update to Intel 20200520 release * Sun May 10 2020 tmb <tmb> 0.20200508-1.mga8.nonfree + Revision: 1582714 - update ICL-U/Y microcode from 00000046 to 00000078
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/usr/share/doc/microcode/README.md /usr/share/doc/microcode/releasenote.md /usr/share/doc/microcode/security.md /usr/share/licenses/microcode /usr/share/licenses/microcode/license
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Fabrice Bellet, Sun Oct 13 11:16:06 2024